CVE-2025-61972 Overview
CVE-2025-61972 affects AMD processors that implement Secure Encrypted Virtualization-Secure Nested Paging (SEV-SNP). The vulnerability stems from missing lock bit protection on North Bridge I/O (NBIO) registers. A local attacker with administrative privileges can leverage this gap to obtain arbitrary System Management Network (SMN) access. Exploitation can lead to arbitrary code execution within the AMD Secure Processor (ASP) and compromise the confidentiality and integrity of SEV-SNP confidential guests. The flaw is tracked under [CWE-1233: Security-Sensitive Hardware Controls with Missing Lock Bit Protection].
Critical Impact
A local admin-privileged attacker can break SEV-SNP guest confidentiality and integrity by executing arbitrary code inside the AMD Secure Processor.
Affected Products
- AMD processors supporting SEV-SNP confidential computing
- AMD platforms exposing NBIO registers without lock bit protection
- Refer to AMD Security Bulletin #3030 for the authoritative product list
Discovery Timeline
- 2026-05-13 - CVE-2025-61972 published to NVD
- 2026-05-13 - Last updated in NVD database
Technical Details for CVE-2025-61972
Vulnerability Analysis
The vulnerability resides in the NBIO subsystem of affected AMD processors. NBIO registers expose configuration interfaces that route to the System Management Network. The SMN is an internal fabric used to configure platform components, including the AMD Secure Processor. Hardware platforms typically protect such sensitive registers with lock bits that, once set during boot, prevent further modification by privileged software. On affected systems, those lock bits are missing or not enforced. The result is a sustained ability for ring-0 software to reach SMN paths that should be sealed off after platform initialization. This breaks a core trust boundary that SEV-SNP relies on to isolate confidential virtual machines from a malicious or compromised hypervisor.
Root Cause
The root cause is the absence of lock bit protection on NBIO registers that gate SMN access. SEV-SNP assumes the host operating system and hypervisor cannot reach the ASP through architectural side paths. Without the lock bits, that assumption fails. This matches the [CWE-1233] weakness pattern, where security-sensitive hardware controls lack the write-protection needed after configuration.
Attack Vector
An attacker requires local execution with high administrative privileges, such as a compromised hypervisor or kernel-level code on the host. From there, the attacker writes to the unprotected NBIO registers to gain arbitrary SMN access. Through SMN, the attacker reaches the AMD Secure Processor and can execute arbitrary code in that trusted context. With code execution in the ASP, the attacker can read or modify SEV-SNP guest memory, defeating the confidentiality and integrity guarantees that protect tenants from the host. Attack complexity is high because the exploit requires precise knowledge of NBIO register layouts and SMN routing on the target silicon. No verified proof-of-concept code is publicly available, and the vulnerability is not listed in the CISA Known Exploited Vulnerabilities catalog.
Detection Methods for CVE-2025-61972
Indicators of Compromise
- Unexpected kernel or hypervisor modules issuing MMIO writes to NBIO register ranges after platform boot completes
- Anomalous SMN transactions originating from host software targeting AMD Secure Processor address spaces
- Unverified or unsigned firmware components loaded on hosts running SEV-SNP confidential workloads
Detection Strategies
- Monitor host kernels and hypervisors for loaded drivers that map NBIO MMIO regions outside of vendor-signed platform code
- Validate platform firmware integrity using attestation and compare measurements against known-good baselines
- Use SEV-SNP guest attestation reports to detect platforms running vulnerable microcode or firmware versions
Monitoring Recommendations
- Track AMD firmware and microcode versions across the fleet and alert on hosts running pre-patch builds
- Audit administrative actions on hypervisor hosts that handle confidential workloads, focusing on driver loads and kernel module insertions
- Correlate guest attestation failures with host configuration changes to identify tampering attempts
How to Mitigate CVE-2025-61972
Immediate Actions Required
- Apply the firmware and microcode updates referenced in AMD Security Bulletin #3030 as soon as vendor builds are available for your platform
- Restrict administrative access on hosts running SEV-SNP confidential VMs to a minimum set of trusted operators
- Require signed and measured boot for all hypervisor hosts that handle confidential computing workloads
Patch Information
AMD addresses the missing lock bit protection through platform firmware updates distributed by OEMs and cloud providers. Consult AMD Security Bulletin #3030 for the list of affected processor families and the corresponding fixed firmware versions. Coordinate deployment with hardware vendors, since NBIO register protection is enforced through platform initialization code shipped in system firmware.
Workarounds
- Reduce exposure by limiting which administrators can load kernel drivers or modify hypervisor configuration on confidential computing hosts
- Require SEV-SNP guest workloads to verify host attestation before releasing sensitive data or keys
- Isolate confidential workloads on dedicated hardware until patched firmware is deployed across the fleet
Disclaimer: This content was generated using AI. While we strive for accuracy, please verify critical information with official sources.
