CVE-2025-9614: PCIe IDE Information Disclosure Flaw

CVE-2025-9614 Overview

CVE-2025-9614 affects the PCI Express (PCIe) Integrity and Data Encryption (IDE) specification maintained by PCI-SIG. The specification provides insufficient guidance on re-keying and stream flushing during device rebinding. As a result, stale write transactions from a previous security context can be processed within a new one. This behavior allows unintended data access across trusted domains and compromises confidentiality and integrity of PCIe IDE-protected traffic.

Critical Impact
Stale write transactions can cross security context boundaries during PCIe device rebinding, exposing data between trusted domains protected by PCIe IDE.

Affected Products

PCI-SIG PCI Express Integrity and Data Encryption (IDE) specification
Devices and platforms implementing PCIe IDE per the affected specification guidance
Confidential computing environments relying on PCIe IDE for TEE Device Interface Security Protocol (TDISP) flows

Discovery Timeline

2025-12-09 - CVE-2025-9614 published to NVD
2026-06-17 - Last updated in NVD database

Technical Details for CVE-2025-9614

Vulnerability Analysis

PCIe IDE encrypts and integrity-protects Transaction Layer Packets (TLPs) between a Root Complex and a PCIe endpoint. Each IDE stream is bound to cryptographic keys tied to a specific security context. When a device is rebound to a different context, both endpoints must flush in-flight transactions and rotate keys before accepting new traffic.

The specification does not fully define this rebinding procedure. Implementations following the specification may forward buffered writes issued under the previous context after the stream has transitioned to a new context. A receiver processes these writes as if they originated from the new tenant, breaking the isolation guarantee that IDE is intended to provide.

The issue is categorized under [NVD-CWE-noinfo] and affects the design of the protocol rather than a single vendor product. Any implementation that follows the ambiguous guidance inherits the flaw.

Root Cause

The root cause is a specification gap. PCIe IDE lacks explicit, normative requirements for atomic transitions between security contexts. There is no mandated ordering between transaction quiescence, buffer flushing, key erasure, and stream re-establishment during device rebinding. This gap creates a window where writes authorized under a prior key stream can be committed under a new one.

Attack Vector

An attacker who can influence device rebinding, such as a malicious virtual machine, tenant, or compromised hypervisor component in a shared confidential computing platform, can time write transactions to persist across a rebind. The stale writes reach a subsequent tenant's memory or device state. Exploitation is remote at the PCIe fabric level and does not require authentication or user interaction, though it does require the ability to trigger or observe rebinding events on the affected fabric.

No public proof-of-concept is available, and the vulnerability is not listed in the CISA Known Exploited Vulnerabilities catalog. The EPSS probability is 0.12%.

Detection Methods for CVE-2025-9614

Indicators of Compromise

Unexpected PCIe TLP write completions arriving immediately after an IDE stream rekey or device rebind event
IDE integrity check failures or MAC mismatches logged by Root Complex or endpoint firmware during context transitions
Anomalous memory writes to regions owned by a newly bound tenant that correlate temporally with a prior tenant's activity

Detection Strategies

Audit platform firmware and BMC logs for PCIe IDE stream state transitions, focusing on rebind, key rotation, and stream teardown events
Correlate confidential VM lifecycle events with PCIe device attach and detach operations to identify unsafe rebinding windows
Enable and monitor TDISP and IDE telemetry exposed by CPU vendors (Intel TDX Connect, AMD SEV-TIO) for out-of-sequence transactions

Monitoring Recommendations

Track firmware and microcode versions across servers hosting PCIe IDE-capable devices and alert on drift from vendor-recommended patched baselines
Ingest hypervisor and platform security processor logs into a centralized data lake for cross-tenant correlation of PCIe rebind events
Baseline normal device rebinding frequency per host and alert on abnormal rebind rates that may indicate probing behavior

How to Mitigate CVE-2025-9614

Immediate Actions Required

Review the PCI-SIG Vulnerability Overview and inventory all PCIe IDE-capable devices and hosts in the environment
Contact device, CPU, and platform vendors for firmware updates that implement the corrected rebinding and flushing sequence
Restrict device rebinding operations to trusted orchestration paths and disable dynamic rebinding where operationally feasible

Patch Information

CVE-2025-9614 is a specification-level flaw. Remediation depends on PCI-SIG publishing updated normative guidance and on device, Root Complex, and platform vendors shipping firmware that enforces atomic key rotation, stream flushing, and transaction quiescence during rebind. Consult the PCI-SIG Specifications Resource and vendor advisories for the specific firmware or ECN references that address the issue.

Workarounds

Pin PCIe devices to a single tenant or security domain for the lifetime of the workload to avoid rebinding entirely
Force a full device reset, including a link-down and re-initialization, between tenants instead of relying on IDE stream rekeying alone
Isolate confidential computing workloads that rely on PCIe IDE onto hosts running only patched firmware and validated hypervisor code paths

bash

# Configuration example: disable dynamic PCIe device rebinding on Linux hosts
# by unbinding the device and blocking automatic driver reattach until
# a full reset has been performed between tenants.
echo 0000:81:00.0 > /sys/bus/pci/devices/0000:81:00.0/driver/unbind
echo 1 > /sys/bus/pci/devices/0000:81:00.0/reset
echo 0000:81:00.0 > /sys/bus/pci/drivers_probe